The present inventioon relates to a semiconductor photoelectric converting device comprising a static induction transistor (hereinafter abbreviated as SIT).
A solid state image sensor comprising a number of semiconductor photoelectric converting devices have been utilized in electronic still cameras, home video cameras, facsimile machines and so on. In the known solid state image sensor use has been widely made of a charge transfer device such as BBD, CCD, or MOS transistor devices. However, the known semiconductor image sensor using such semiconductor devices has drawbacks such as charge leakage during transportation of the signal charges, a low light detection sensitivity and a low integration density.
In order to remove all the above mentioned drawbacks there has been developed a solid state image sensor utilizing SITs. The SIT is a kind of a phototransistor having a photoelectric converting function and a photocarrier amplifying function and is superior to a field effect transistor and junction transistor in view of its high input impedance, high operation speed, non-saturation, low noise and low power consumption. Therefore, when a solid state image sensor is constructed by using SITs as photosensitive elements, it is possible to obtain a semiconductor image sensor having high sensitivity, high speed response and wide dynamic range. Such a semiconductor image sensor has been described in, for instance Japanese Patent Laid-open Publication No. 15,229/80.
FIG. 1 is a cross sectional view showing an SIT forming a pixel of the known solid state image sensor described in the above-referenced Laid-open Publication. This SIT is of the vertical type and comprises an n.sup.+ substrate 1 constituting a drain region, and an n.sup.- epitaxial layer 2 formed on the substrate 1, the epitaxial layer 2 forming a channel region. The SIT further comprises a source region 3 constructed by an n.sup.+ region 3 which is formed in the surface of epitaxial layer 2. In the surface of epitaxial layer 2, there is further formed a p.sup.+ signal storing gate region 4 which surrounds the source region 3. On the gate region 4 is formed an insulating film 5 and a gate electrode 6. In this manner, there is formed a metal-insulator-gate region construction, i.e. MIS gate construction. The n.sup.- epitaxial layer 2 forming the channel region has such a low impurity concentration such that the channel region has been depleted to form a high potential barrier and has been pinched-off thereby even though a bias voltage of zero volts is applied to the gate region 6.
Now the operational principle of the SIT will be explained hereinafter. When light input is made incident upon the channel regioon 2 and gate region 4, while a bias voltage is not applied across the drain and source, electronhole pairs are generated in the channel and gate regions, the holes are stored in the gate region 4 the electrons are flow to the earth via the drain region 1. The holes stored in the gate region 4 in response to the light input increases the potential of the gate and thus the potential barrier in the channel region 2 is decreased accordingly. When a bias is applied across the drain and source and a forward voltage is applied to the gate electrode 6, a current flows between the drain and source in accordance with the amount of holes stored in the gate region 4. In this manner, an output which is amplified with respect to the light input can be obtained. Usually the light amplification S is larger than 10.sup.3, and thus the SIT has a higher sensitivity than the known bipolar transistor by more than ten times. Generally the light amplification S can be represented as follows. ##EQU1## wherein 2a is an inner diameter of the gate region, l.sub.1 is a depth of the gate region and l.sub.2 is a distance between the gate and drain regions. As can be understood from the above equation, in order to make larger the light amplification S, it is necessary to decrease the inner diameter 2a as well as to increase the thickness of the epitaxial layer 2 and the depth of the gate region 4. For instance, in order to obtain the light amplifications S of 10.sup.3 -10.sup.4, it is usually necessary to satisfy such conditions that l.sub.1 =2-3 .mu.m and l.sub.2 =5-6 .mu.m.
In the solid state image sensor shown in FIG. 1, between adjacent SITs is formed an isolation gate region 7 for isolating the signal charges in respective SITs from one another. In general, the isolation gate region 7 is formed by oxide film, diffused region or V-shaped recess. Usually, the isolation region 7 extends from the surface of epitaxial layer 2 to the surface of substrate 1 and therefore, if the epitaxial layer 2 has a large thickness, the formation of the isolation region 7 becomes much more difficult. On the other hand, in order to obtain a higher light amplification S, it is necessary to make the gate region 4 deeper, but in practice, the gate 4 cannot be made deeper by the diffusion method. Moreover, if the gate region 4 has a larger depth, there might occur an absorption of light therein and the spectroscopic sensitivity of the image sensor becomes worse. In this manner, in the known solid state image sensor having the vertical type SITs, the sensitivity is inherently limited due to its constructional feature discussed above.